IEEE - Institute of Electrical and Electronics Engineers, Inc. - A proposed methodology to improve UVM-based test generation and coverage closure

2015 10th International Design & Test Symposium (IDT)

Author(s): Khaled Fathy ; Khaled Salah ; Rafik Guindi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2015
Conference Location: Amman, Jordan
Conference Date: 14 December 2015
Page(s): 147 - 148
ISBN (Electronic): 978-1-4673-9994-4
ISBN (USB): 978-1-4673-9993-7
DOI: 10.1109/IDT.2015.7396754
Regular:

Verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and... View More

Advertisement