IEEE - Institute of Electrical and Electronics Engineers, Inc. - Communication scheduling and buslet synthesis for low-interconnect HLS designs

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Author(s): Enzo Tartaglione ; Shantanu Dutt
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2015
Conference Location: Austin, TX, USA
Conference Date: 2 November 2015
Page(s): 86 - 93
ISBN (Electronic): 978-1-4673-8388-2
ISBN (USB): 978-1-4673-8389-9
DOI: 10.1109/ICCAD.2015.7372554
Regular:

Current nanoscale designs are highly interconnect dominated, taking about 70% of the chip area. Interconnects also consume significant dynamic power, and about 60% of signal delays. It is thus... View More

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