IEEE - Institute of Electrical and Electronics Engineers, Inc. - A virtual platform for exploring hierarchical interconnection for many-accelerator systems

2015 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

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The advent of many-accelerator Systems-on-Chip (SoC), as a result of the ever increasing demands for high performance and energy efficiency, has lead to the need for new interconnection schemes among the system components, which minimize the communication overhead. Towards this need, Hierarchical Networks-on-Chip (HNoCs) can provide an efficient communication paradigm for such systems: Each node is an autonomous sub-network including the hardware accelerators needed by the respective application thread, thus retaining data locality and minimizing congestion. However, HNoC design may lead to exponential increase in the design space size, due to the numerous parameter combinations of the sub-networks and the overall HNoC. In addition, the need for a prototyping framework supporting HNoC simulation with real stimuli is crucial for the accurate system evaluation. Therefore, the goal of this paper is to present (a) a SystemC framework for cycle-accurate simulation of Hierarchical NoCs, accompanied with a NoC API for node mapping on the HNoC; and (b) an exploration flow that targets to reduce the increased design space size. By using the Rician Denoising algorithm for MRI scans as a case study, the proposed DSE flow could achieve up to 2× and 1.48× time and power improvements respectively, as compared to a typical DSE flow.

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Author(s):	Efstathios Sotiriou-Xanthopoulos ; Sotirios Xydis ; Kostas Siozios ; George Economakos
Publisher:	IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date:	1 July 2015
Conference Location:	Samos, Greece
Conference Date:	19 July 2015
Page(s):	384 - 389
ISBN (Electronic):	978-1-4673-7311-1
DOI:	10.1109/SAMOS.2015.7363703

IEEE - Institute of Electrical and Electronics Engineers, Inc.