IEEE - Institute of Electrical and Electronics Engineers, Inc. - Dual-mode double precision / two-parallel single precision floating point multiplier architecture

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

Author(s): Manish Kumar Jaiswal ; Hayden K.-H So
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2015
Conference Location: Daejeon, South Korea
Conference Date: 5 October 2015
Page(s): 213 - 218
ISBN (Electronic): 978-1-4673-9140-5
ISBN (USB): 978-1-4673-9139-9
ISSN (Electronic): 2324-8440
DOI: 10.1109/VLSI-SoC.2015.7314418
Regular:

Floating point multiplication is an integral part of any contemporary computing system. This paper presents a configurable dual-mode double precision floating point multiplier architecture, which... View More

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