IEEE - Institute of Electrical and Electronics Engineers, Inc. - Cost reduction of system-level tests with stressed structural tests and SVM

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

Author(s): Jing-Jia Liou ; Meng-Ta Hsieh ; Jun-Fei Cherng ; Harry H. Chen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2015
Conference Location: Daejeon, South Korea
Conference Date: 5 October 2015
Page(s): 177 - 182
ISBN (Electronic): 978-1-4673-9140-5
ISBN (USB): 978-1-4673-9139-9
ISSN (Electronic): 2324-8440
DOI: 10.1109/VLSI-SoC.2015.7314412
Regular:

System tests with boards are applied to capture defects in functional modes. Yet, these tests are usually costly with limitation on the production throughputs. Stressed structural tests (patterns... View More

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