IEEE - Institute of Electrical and Electronics Engineers, Inc. - Circuit performance optimization for local intra-die process variations using a gate selection metric

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

Author(s): Victor Champac ; Alejandra Nicte-ha Reyes ; Andres F. Gomez
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2015
Conference Location: Daejeon, South Korea
Conference Date: 5 October 2015
Page(s): 165 - 170
ISBN (Electronic): 978-1-4673-9140-5
ISBN (USB): 978-1-4673-9139-9
ISSN (Electronic): 2324-8440
DOI: 10.1109/VLSI-SoC.2015.7314410
Regular:

Process variations are imposing strong limits to performance of digital circuits at gigascale integration; they are classified in two types: inter-die and intra-die variations. Moreover, intra-die... View More

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