IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

Author(s): Jaehyun Park ; Donghwa Shin ; Hyung Gyu Lee
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2015
Conference Location: Daejeon, South Korea
Conference Date: 5 October 2015
Page(s): 104 - 109
ISBN (Electronic): 978-1-4673-9140-5
ISBN (USB): 978-1-4673-9139-9
ISSN (Electronic): 2324-8440
DOI: 10.1109/VLSI-SoC.2015.7314400
Regular:

Phase change memory (PCM) is an attractive candidate for the future memory, but it still has several limitations to overcome such as write latency and long-term endurance. A large body of... View More

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