IEEE - Institute of Electrical and Electronics Engineers, Inc. - The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

Author(s): A.L. Butler ; D.J. Foster
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 1985
Volume: 20
Page(s): 70 - 75
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/JSSC.1985.1052278
Regular:

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-/spl mu/m transistors. This can be readily achieved with highly doped... View More

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