IEEE - Institute of Electrical and Electronics Engineers, Inc. - Timing model for two stage buffer and its application in ECSM characterization

2015 19th International Symposium on VLSI Design and Test (VDAT)

Author(s): Yogesh Chaurasiya ; Surabhi Bhargava ; Arvind Sharma ; Baljit Kaur ; Bulusu Anand
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2015
Conference Location: Ahmedabad, India
Conference Date: 26 June 2015
Page(s): 1 - 6
ISBN (CD): 978-1-4799-1742-6
ISBN (Electronic): 978-1-4799-1743-3
DOI: 10.1109/ISVDAT.2015.7208075
Regular:

At nanometer technology nodes, variability is a major roadblock for circuit performance. This has made timing estimation of circuits a tedious task. Effective Current Source Model (ECSM)... View More

Advertisement