IEEE - Institute of Electrical and Electronics Engineers, Inc. - Area optimized CMOS layouts of a 50 Gb/s low power 4:1 multiplexer

2015 19th International Symposium on VLSI Design and Test (VDAT)

Author(s): Vibhor Pareek ; Gaurvi Goyal
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2015
Conference Location: Ahmedabad, India
Conference Date: 26 June 2015
Page(s): 1 - 6
ISBN (CD): 978-1-4799-1742-6
ISBN (Electronic): 978-1-4799-1743-3
DOI: 10.1109/ISVDAT.2015.7208054
Regular:

In this work, novel layouts of a 4:1 CMOS transmission gate multiplexer are presented. The proposed layouts are realized by following the design rules for 45 nm and 90 nm CMOS processes, with a... View More

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