IEEE - Institute of Electrical and Electronics Engineers, Inc. - GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis

2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE)

Author(s): Pallabi Sarkar ; Anirban Sengupta ; Mrinal Kanti Naskar
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2015
Conference Location: Halifax, NS, Canada
Conference Date: 3 May 2015
Page(s): 75 - 80
ISBN (Electronic): 978-1-4799-5829-0
ISBN (Paper): 978-1-4799-5827-6
ISSN (Paper): 0840-7789
DOI: 10.1109/CCECE.2015.7129163
Regular:

A novel solution to the problem of integrated exploration of datapath resource configuration and loop unrolling factor (UF) for control data flow graphs (CDFGs) during high level synthesis (HLS)... View More

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