IEEE - Institute of Electrical and Electronics Engineers, Inc. - An effective ATPG flow for Gate Delay Faults

2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

Author(s): A. Bosio ; L. Dilillo ; P. Girard ; A. Virazel ; P. Bernardi ; M. Sonza Reorda
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2015
Conference Location: Naples, Italy
Conference Date: 21 April 2015
Page(s): 1 - 6
ISBN (Electronic): 978-1-4799-1999-4
DOI: 10.1109/DTIS.2015.7127350
Regular:

This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of... View More

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