IEEE - Institute of Electrical and Electronics Engineers, Inc. - Sparse FIR filters and the impact on FPGA area usage

2008 42nd Asilomar Conference on Signals, Systems and Computers

Author(s): S.G. Patronis ; L.S. DeBrunner
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2008
Conference Location: Pacific Grove, CA, USA
Conference Date: 26 October 2008
Page(s): 1,862 - 1,866
ISBN (CD): 978-1-4244-2941-7
ISBN (Paper): 978-1-4244-2940-0
ISSN (Paper): 1058-6393
DOI: 10.1109/ACSSC.2008.5074751
Regular:

In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area and speed up computations, but when... View More

Advertisement