IEEE - Institute of Electrical and Electronics Engineers, Inc. - Networks-on-Chip topology generation techniques: Area and delay evaluation

3rd International Design and Test Workshop (IDT 2008)

Author(s): A.A. Morgan ; H. Elmiligi ; M. Watheq El-Kharashi ; F. Gebali
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Monastir, Tunisia
Conference Date: 20 December 2008
Page(s): 33 - 38
ISBN (CD): 978-1-4244-3478-7
ISBN (Paper): 978-1-4244-3479-4
DOI: 10.1109/IDT.2008.4802460
Regular:

Networks-on-Chip (NoC) topology generation faces a trade-off between cost and performance. In this paper, we evaluate different custom and standard NoC topology generation techniques with respect... View More

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