IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

IEDM 2008. IEEE International Electron Devices Meeting

Author(s): C.-H. Jan ; P. Bai ; S. Biswas ; M. Buehler ; Z.-P. Chen ; G. Curello ; S. Gannavaram ; W. Hafez ; J. He ; J. Hicks ; U. Jalan ; N. Lazo ; J. Lin ; N. Lindert ; C. Litteken ; M. Jones ; M. Kang ; K. Komeyli ; A. Mezhiba ; S. Naskar ; S. Olson ; J. Park ; R. Parker ; L. Pei ; I. Post ; N. Pradhan ; C. Prasad ; M. Prince ; J. Rizk ; G. Sacks ; H. Tashiro ; D. Towner ; C. Tsai ; Y. Wang ; L. Yang ; J.-Y. Yeh ; J. Yip ; K. Mistry
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: San Francisco, CA, USA
Conference Date: 15 December 2008
Page(s): 1 - 4
ISBN (CD): 978-1-4244-2378-1
ISBN (Paper): 978-1-4244-2377-4
ISSN (Paper): 8164-2284
DOI: 10.1109/IEDM.2008.4796772
Regular:

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of... View More

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