IEEE - Institute of Electrical and Electronics Engineers, Inc. - Thermal-Electrical Co-simulation for Wafer-level Chip Scale Package Maximum Bearing Current

2008 10th Electronics Packaging Technology Conference (EPTC 2008)

Author(s): Rui-Yu ; Shu-Qiang Zhang ; Chang-Lin Yeh ; Chi-Sheng Chung ; Chih-Pin Hung
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Singapore, Singapore
Conference Date: 9 December 2008
Page(s): 860 - 863
ISBN (CD): 978-1-4244-2118-3
ISBN (Paper): 978-1-4244-2117-6
DOI: 10.1109/EPTC.2008.4763538
Regular:

As the trend of smaller and higher density packaging technology developing, the wafer-level chip scale package (WLCSP) is becoming the popular choice for device assembly. While many high... View More

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