IEEE - Institute of Electrical and Electronics Engineers, Inc. - Development of Evaluation Approach for Delamination Considering Micro-Scale Interfacial Layer Structure between Resin and Silicon

2008 10th Electronics Packaging Technology Conference (EPTC 2008)

Author(s): T. Matsumoto ; Qiang Yu ; T. Shibutani ; T. Matsuzaki
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Singapore, Singapore
Conference Date: 9 December 2008
Page(s): 816 - 820
ISBN (CD): 978-1-4244-2118-3
ISBN (Paper): 978-1-4244-2117-6
DOI: 10.1109/EPTC.2008.4763532
Regular:

Interconnect technology is the key to the reliability of electronic devices. Electronic components are soldered to a printed circuit board (PCB). Major failure mode is thermal fatigue of solder... View More

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