IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design, Assembly and Reliability of Large Die (21 x 21mm2) and Fine-pitch (150pm) Cu/Low-K Flip Chip Package

2008 10th Electronics Packaging Technology Conference (EPTC 2008)

Author(s): Y.Y. Ong ; K. Vaidyanathan ; S.W. Ho ; V.N. Sekhar ; M.C. Jong ; L.C. Wai ; V.S. Rao ; V. Sheng ; J. Ong ; X. Ong ; X. Zhang ; Y.U. Seung ; J. Lau ; Y.K. Lim ; D. Yeo ; K.C. Chan ; Z. Yanfeng ; J.B. Tan ; D.K. Sohn
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Singapore, Singapore
Conference Date: 9 December 2008
Page(s): 613 - 619
ISBN (CD): 978-1-4244-2118-3
ISBN (Paper): 978-1-4244-2117-6
DOI: 10.1109/EPTC.2008.4763501
Regular:

This paper focused on design, assembly and reliability assessments of 21 × 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ¿m bump pitch. Metal redistribution layer (RDL) and... View More

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