IEEE - Institute of Electrical and Electronics Engineers, Inc. - Effects of gate length on the performance of a top gate silicon nanowire on insulator (SOI) transistor

2008 IEEE International Conference on Electron Devices and Solid-State Circuits

Author(s): S. Bhowmick ; R.N. Sajjad ; Q. Khosru
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Hong Kong, China
Conference Date: 8 December 2008
Page(s): 1 - 4
ISBN (CD): 978-1-4244-2540-2
ISBN (Paper): 978-1-4244-2539-6
DOI: 10.1109/EDSSC.2008.4760708
Regular:

The effects of gate length Lg on the performance of a top gate silicon nanowire on insulator transistor are studied using three dimensional quantum simulation. From the study it is... View More

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