IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology

2008 IEEE International Conference on Electron Devices and Solid-State Circuits

Author(s): Bo Wang ; Dianyong Chen ; A. Liao ; Bangli Liang ; T. Kwasniewski
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Hong Kong, China
Conference Date: 8 December 2008
Page(s): 1 - 4
ISBN (CD): 978-1-4244-2540-2
ISBN (Paper): 978-1-4244-2539-6
DOI: 10.1109/EDSSC.2008.4760694
Regular:

In this paper, we discuss an optimized current-mode logic (CML) circuit design technique for high-speed backplane transmission. The inductorless CML circuits are extensively used in high-speed... View More

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