IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of a Switch-Level Analog Model for Verilog

2008 IEEE International Behavioral Modeling and Simulation Workshop

Author(s): T.J. Sheffler
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2008
Conference Location: San Jose, CA, USA
Conference Date: 25 September 2008
Page(s): 118 - 123
ISBN (Paper): 978-1-4244-2896-0
DOI: 10.1109/BMAS.2008.4751252
Regular:

This paper describes a modeling extension to Verilog called "Switch-Level Analog." It is inspired by the switch-level transistor modeling facility of Verilog, but extends the value domain from... View More

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