IEEE - Institute of Electrical and Electronics Engineers, Inc. - Modelling and compensating for clock skew variability in FPGAs

2008 International Conference on Field-Programmable Technology

Author(s): P. Sedcole ; J.S. Wong ; P.Y.K. Cheung
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2008
Conference Location: Taipei, Taiwan
Conference Date: 8 December 2008
Page(s): 217 - 224
ISBN (CD): 978-1-4244-2796-3
ISBN (Paper): 978-1-4244-3783-2
DOI: 10.1109/FPT.2008.4762386
Regular:

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic... View More

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