IEEE - Institute of Electrical and Electronics Engineers, Inc. - Modeling and reduction of complex timing constraints in high performance digital circuits

2008 IEEE International Conference on Computer Design

Author(s): N. Veerapaneni ; C.Y.R. Chen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2008
Conference Location: Lake Tahoe, CA, USA
Conference Date: 12 October 2008
Page(s): 544 - 550
ISBN (CD): 978-1-4244-2658-4
ISBN (Paper): 978-1-4244-2657-7
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.2008.4751914
Regular:

Complex timing constraints that refer to multiple clocks and/or edges are often used in the design of modern high performance processors. Such constraints complicate the design of downstream... View More

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