IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective

2008 IEEE International Conference on Computer Design

Author(s): V. Packirisamy ; Yangchun Luo ; Wei-Lung Hung ; A. Zhai ; Pen-Chung Yew ; Tin-Fook Ngai
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2008
Conference Location: Lake Tahoe, CA, USA
Conference Date: 12 October 2008
Page(s): 286 - 293
ISBN (CD): 978-1-4244-2658-4
ISBN (Paper): 978-1-4244-2657-7
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.2008.4751875
Regular:

Computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase stalled in early 2000psilas. However, because of the lack of compilers and other related... View More

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