IEEE - Institute of Electrical and Electronics Engineers, Inc. - Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities

2008 IEEE International Conference on Computer Design

Author(s): K. Shi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2008
Conference Location: Lake Tahoe, CA, USA
Conference Date: 12 October 2008
Page(s): 170 - 175
ISBN (CD): 978-1-4244-2658-4
ISBN (Paper): 978-1-4244-2657-7
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.2008.4751857
Regular:

This paper presents two area and power-delay efficient state retention pulsed flops with scan and reset capabilities for sub-90 nm production low-power designs. The proposed flops also mitigate... View More

Advertisement