IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 60 ns 256Kx1 bit DRAM using LD/SUP 3/ technology and double-level metal interconnection

Author(s): R.A. Kertis ; K.J. Fitzpatrick ; K.B. Ohri
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 1984
Volume: 19
Page(s): 585 - 590
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/JSSC.1984.1052193
Regular:

A high-speed 256K/spl times/1-bit DRAM, using new circuit design techniques and a scaled n-channel process, has been developed. A row access time of 60 ns has been achieved through the use of... View More

Advertisement