IEEE - Institute of Electrical and Electronics Engineers, Inc. - The design and transport latency analysis of a locality-aware network on chip architecture

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): Chung-Ping Young ; Chung-Chu Chia ; Yen-Bor Lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 1,272 - 1,275
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746259
Regular:

The major drawback of an on-chip network is the strongly decreased timing predictability due to the dynamic routing. While for some special applications, such as distributed shared memory (DSM)... View More

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