IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): Geng Luo-Feng ; Du Gao-ming ; Zhang Duo-Li ; Gao Ming-Lun ; Hou Ning ; Song Yu-Kun
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 1,264 - 1,267
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746257
Regular:

The network on chips (NoCs) is a promising solution for future on-chip interconnection. In this area, fast and accurate performance evaluation and design space exploration for the NoCs are... View More

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