IEEE - Institute of Electrical and Electronics Engineers, Inc. - On output reorder buffer design of bit reversed pipelined continuous data FFT architecture

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): T.S. Chakraborty ; S. Chakrabarti
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 1,132 - 1,135
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746224
Regular:

Fast Fourier transform (FFT) is the reduced complexity algorithm to implement highly computational complex discrete Fourier transform (DFT). Cooley-Tookey based decomposition method is the most... View More

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