IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low-jitter PLL by interpolate compensation

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): Y. Nakanishi ; F. Kobayashi ; H. Kondoh
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 1,078 - 1,081
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746211
Regular:

In order to reduce jitters, vital characteristics in some PLL applications, a PLL with compensator and interpolative loop is proposed. This PLL improves the problem that conventional PLL cannot... View More

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