IEEE - Institute of Electrical and Electronics Engineers, Inc. - A second-order gate delay modeling method with an efficient sensitivity analysis

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): Sangwoo Han ; Yooseong Kim ; Woosick Choi ; Inho Shin ; Youngdoo Choi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 1,008 - 1,011
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746195
Regular:

As CMOS technology scales, to consider process variation becomes increasingly challenging. Statistical gate delay model is widely used technique to analyze the influence of process variation on... View More

Advertisement