IEEE - Institute of Electrical and Electronics Engineers, Inc. - A design method for skew tolerant latch design

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): Y. Nakamura
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 356 - 359
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746033
Regular:

This paper describes a new design method for skew-tolerant latch design (STLD) and evaluation on a commercial chip design. The conventional edge-triggered flip-flop (FF) design methods using clock... View More

Advertisement