IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multi-V th FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): S.A. Tawfik ; V. Kursun
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 348 - 351
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4746031
Regular:

Brute-force sequential circuits with reduced clock load and simpler circuitry are widely used in the state-of-the-art integrated circuits. In this paper, new multi threshold voltage... View More

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