IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low-latency VLSI architecture of a 3-input floating-point adder

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): A. Guntoro ; M. Glesner
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 180 - 183
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4745990
Regular:

In this paper, we present the design and the implementation of a 3-input IEEE 754-compliant floating-point adder. 3 level pipeline stages are used in order to distribute the critical paths and to... View More

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