IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-speed and low-power serial accumulator for serial/parallel multiplier

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Author(s): M.R. Meher ; Ching-Chuen Jong ; Chip-Hong Chang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2008
Conference Location: Macao, China
Conference Date: 30 November 2008
Page(s): 176 - 179
ISBN (Paper): 978-1-4244-2341-5
ISBN (Online): 978-1-4244-2342-2
DOI: 10.1109/APCCAS.2008.4745989
Regular:

This paper presents a new approach to serial/parallel multiplier design by using parallel 1psilas counters to accumulate the binary partial product bits. The 1psilas in each column of the partial... View More

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