IEEE - Institute of Electrical and Electronics Engineers, Inc. - Minimal complexity low-latency architectures for Viterbi decoders

2008 IEEE Workshop on Signal Processing Systems

Author(s): Renfei Liu ; K.K. Parhi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2008
Conference Location: Washington, DC, USA
Conference Date: 8 October 2008
Page(s): 140 - 145
ISBN (CD): 978-1-4244-2924-0
ISBN (Paper): 978-1-4244-2923-3
ISSN (Paper): 1520-6130
DOI: 10.1109/SIPS.2008.4671752
Regular:

For Viterbi decoders, high throughput rate is achieved by applying look-ahead techniques in the add-compare-select unit, which is the system speed bottleneck. Look-ahead techniques combine... View More

Advertisement