IEEE - Institute of Electrical and Electronics Engineers, Inc. - Using SystemC for an extended MATLAB/Simulink verification flow

2008 Forum on Specification, Verification & Design Languages (FDL)

Author(s): K. Hylla ; J.-H. Oetjens ; W. Nebel
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2008
Conference Location: Stuttgart, Germany
Conference Date: 23 September 2008
Page(s): 221 - 226
ISBN (CD): 978-1-4244-2266-1
ISBN (Paper): 978-1-4244-2264-7
DOI: 10.1109/FDL.2008.4641449
Regular:

Functional verification is a major part of todaypsilas system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using... View More

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