IEEE - Institute of Electrical and Electronics Engineers, Inc. - Wafer-scale integration of analog neural networks

2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence)

Author(s): J. Schemmel ; J. Fieres ; K. Meier
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Hong Kong, China
Conference Date: 1 June 2008
Page(s): 431 - 438
ISBN (CD): 978-1-4244-1821-3
ISBN (Paper): 978-1-4244-1820-6
ISSN (Paper): 1098-7576
DOI: 10.1109/IJCNN.2008.4633828
Regular:

This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time analog neurons with up to 16 k... View More

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