IEEE - Institute of Electrical and Electronics Engineers, Inc. - A piecewise transistor-level simulation technique for the steady state and phase noise analysis of integer N PLLs

2008 IEEE MTT-S International Microwave Symposium Digest - MTT 2008

Author(s): Bo Wang ; Edouard Ngoya
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Atlanta, GA, USA, USA
Conference Date: 15 June 2008
Page(s): 1,429 - 1,432
ISBN (CD): 978-1-4244-1781-0
ISBN (Paper): 978-1-4244-1780-3
ISSN (Paper): 0149-645X
DOI: 10.1109/MWSYM.2008.4633047
Regular:

Brute force transistor-level simulation of PLL is precise but suffers long simulation time and convergence problems, both with time domain and harmonic-balance techniques. On the other hand common... View More

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