IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performance optimization by track swapping on critical paths utilizing random variations for FPGAS

2008 International Conference on Field Programmable Logic and Applications (FPL)

Author(s): Y. Sugihara ; Y. Kume ; K. Kobayashi ; H. Onodera
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2008
Conference Location: Heidelberg, Germany
Conference Date: 8 September 2008
Page(s): 503 - 506
ISBN (CD): 978-1-4244-1961-6
ISBN (Paper): 978-1-4244-1960-9
DOI: 10.1109/FPL.2008.4629994
Regular:

Since FPGAs in future deep sub-micron processes will suffer from drastic speed and yield losses caused by device variations, we propose variation-aware reconfiguration that utilizes these... View More

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