IEEE - Institute of Electrical and Electronics Engineers, Inc. - Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

2008 International Conference on Field Programmable Logic and Applications (FPL)

Author(s): Meikang Qiu ; Jiande Wu ; Chun Jason Xue ; Jingtong Aaron Hu ; Wei-Che Tseng ; E.H.-M. Sha
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2008
Conference Location: Heidelberg, Germany
Conference Date: 8 September 2008
Page(s): 459 - 462
ISBN (CD): 978-1-4244-1961-6
ISBN (Paper): 978-1-4244-1960-9
DOI: 10.1109/FPL.2008.4629983
Regular:

Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing... View More

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