IEEE - Institute of Electrical and Electronics Engineers, Inc. - FPGA implementation of a self-organized map with on-chip learning

11th International Conference on Optimization of Electrical and Electronic Equipment. OPTIM 2008

Author(s): A. Tisan ; S. Oniga ; C. Gavrincea ; A. Buchman
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2008
Conference Location: Brasov, Romania
Conference Date: 22 May 2008
Page(s): 81 - 86
ISBN (CD): 978-1-4244-1545-8
ISBN (Paper): 978-1-4244-1544-1
DOI: 10.1109/OPTIM.2008.4602503
Regular:

In this paper we propose a method to implement SOM neural network in FPGA circuits: a self organized map neural network with on-chip learning algorithm. The method implies the building of a neural... View More

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