IEEE - Institute of Electrical and Electronics Engineers, Inc. - Statistical leakage modeling in CMOS logic gates considering process variations

2008 IEEE International Conference on IC Design and Technology & Tutorial (ICICDT)

Author(s): C. D'Agostino ; P. Flatresse ; E. Beigne ; M. Belleville
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Austin, TX, USA
Conference Date: 2 June 2008
Page(s): 301 - 304
ISBN (CD): 978-1-4244-1811-4
ISBN (Paper): 978-1-4244-1810-7
DOI: 10.1109/ICICDT.2008.4567301
Regular:

The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread... View More

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