IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

2008 IEEE International Conference on IC Design and Technology & Tutorial (ICICDT)

Author(s): K. Itoh
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Austin, TX, USA
Conference Date: 2 June 2008
Page(s): 177 - 180
ISBN (CD): 978-1-4244-1811-4
ISBN (Paper): 978-1-4244-1810-7
DOI: 10.1109/ICICDT.2008.4567273
Regular:

The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by... View More

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