IEEE - Institute of Electrical and Electronics Engineers, Inc. - Process variability-induced timing failures— A challenge in nanometer CMOS low-power design

2008 IEEE International Conference on IC Design and Technology & Tutorial (ICICDT)

Author(s): Xiaonan Zhang ; Xiaoliang Bai
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Austin, TX, USA
Conference Date: 2 June 2008
Page(s): 159 - 162
ISBN (CD): 978-1-4244-1811-4
ISBN (Paper): 978-1-4244-1810-7
DOI: 10.1109/ICICDT.2008.4567269
Regular:

This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd... View More

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