IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

2008 IEEE International Conference on IC Design and Technology & Tutorial (ICICDT)

Author(s): N. Collaert ; K. von Arnim ; R. Rooyackers ; T. Vandeweyer ; A. Mercha ; B. Parvais ; L. Witters ; A. Nackaerts ; E. Altamirano Sanchez ; M. Demand ; A. Hikavyy ; S. Demuynck ; K. Devriendt ; F. Bauer ; I. Ferain ; A. Veloso ; K. De Meyer ; S. Biesemans ; M. Jurczak
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Austin, TX, USA
Conference Date: 2 June 2008
Page(s): 59 - 62
ISBN (CD): 978-1-4244-1811-4
ISBN (Paper): 978-1-4244-1810-7
DOI: 10.1109/ICICDT.2008.4567246
Regular:

While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors,... View More

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