IEEE - Institute of Electrical and Electronics Engineers, Inc. - Jitter suppressed on-chip clock distribution using package plane cavity resonance

2008 1st Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC) & 19th International Zurich Symposium on Electromagnetic Compatibility

Author(s): Woojin Lee ; Chunghyun Ryu ; Jongbae Park ; Joungho Kim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2008
Conference Location: Singapore, Singapore
Conference Date: 19 May 2008
Page(s): 427 - 430
ISBN (CD): 978-981-08-0629-3
DOI: 10.1109/APEMC.2008.4559903
Regular:

This paper presents a chip-package hybrid clock distribution network using package or PCB plane cavity resonance. This structure enhances Q factor through low loss plane cavity and lowers phase... View More

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