IEEE - Institute of Electrical and Electronics Engineers, Inc. - Evaluation of power supply noise in CMOS and low noise logic cells

2008 1st Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC) & 19th International Zurich Symposium on Electromagnetic Compatibility

Author(s): Junfeng Zhou ; Wim Dehaene
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2008
Conference Location: Singapore, Singapore
Conference Date: 19 May 2008
Page(s): 12 - 15
ISBN (CD): 978-981-08-0629-3
DOI: 10.1109/APEMC.2008.4559799
Regular:

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in... View More

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