IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient Bit-Level Model Reductions for Automated Hardware Verification

2008 15th International Symposium on Temporal Representation and Reasoning (TIME '08)

Author(s): S. Tverdyshev ; E. Alkassar
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2008
Conference Location: Montreal, QC, Canada
Conference Date: 16 June 2008
Page(s): 164 - 172
ISBN (Paper): 978-0-7695-3181-6
ISSN (Paper): 1530-1311
DOI: 10.1109/TIME.2008.11
Regular:

Transition systems which do not perform domain-specific operations on their state variables can be efficiently reduced. We present two different algorithms which automatically eliminate... View More

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