IEEE - Institute of Electrical and Electronics Engineers, Inc. - A simulation study of the bit interference effects in an ultra-thin-body, double-gate, trapped-charge-storage type non-volatile memory cell

2008 IEEE International Reliability Physics Symposium (IRPS)

Author(s): Wen-Jer Tsai ; T.F. Ou ; J.S. Huang ; T.C. Lu ; K.C. Chen ; Chih-Yuan Lu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2008
Conference Location: Phoenix, AZ, USA
Conference Date: 27 April 2008
Page(s): 697 - 698
ISBN (CD): 978-1-4244-2050-6
ISBN (Paper): 978-1-4244-2049-0
DOI: 10.1109/RELPHY.2008.4558994
Regular:

Bit interference effects in an ultra-thin body, double-gate, trapped-charge-storage type non-volatile memory cell are investigated through two-dimensional device simulations. Though such... View More

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